A Quantitative Analysis of Processor Memory Bandwidth of an FPGA-MPSoC
| dc.contributor.author | Drehmel, Robert | |
| dc.contributor.author | Göbel, Matthias | |
| dc.contributor.author | Juurlink, Ben | |
| dc.date.accessioned | 2020-08-25T09:05:22Z | |
| dc.date.available | 2020-08-25T09:05:22Z | |
| dc.date.issued | 2020 | |
| dc.description.abstract | System designers have to choose between a variety of different memories available on modern FPGA-MPSoCs. Our intention is to shed light on the achievable bandwidth when accessing them under diverse circumstances and to hint at their suitability for general-purpose applications. We conducted a systematic quantitative analysis of the memory bandwidth of two processing units using a sophisticated standalone bandwidth measurement tool. The results show a maximum cacheable memory bandwidth of 7.11 GiB/s for reads and 11.78 GiB/s for writes for the general-purpose processing unit, and 2.56 GiB/s for reads and 1.83 GiB/s writes for the special-purpose (real-time) processing unit. In contrast, the achieved non-cacheable read bandwidth lies between 60 MiB/s and 207 MiB/s, with an outlier of 2.67 GiB/s. We conclude that for most applications, relying on DRAM and hardware cache coherency management is the best choice in terms of benefit-cost ratio. | en |
| dc.identifier.pissn | 0177-0454 | |
| dc.identifier.uri | https://dl.gi.de/handle/20.500.12116/33868 | |
| dc.language.iso | en | |
| dc.publisher | Gesellschaft für Informatik e.V., Fachgruppe PARS | |
| dc.relation.ispartof | PARS-Mitteilungen: Vol. 35, Nr. 1 | |
| dc.title | A Quantitative Analysis of Processor Memory Bandwidth of an FPGA-MPSoC | en |
| dc.type | Text/Journal Article | |
| gi.citation.endPage | 94 | |
| gi.citation.publisherPlace | Berlin | |
| gi.citation.startPage | 85 |
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