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A Fault-Tolerant Processor Architecture

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dc.contributor.authorBouajila, Abdelmajid
dc.contributor.authorSommer, Thomas
dc.contributor.authorZeppenfeld, Johannes
dc.contributor.authorStechele, Walter
dc.contributor.authorHerkersdorf, Andreas
dc.date.accessioned2017-12-06T08:58:48Z
dc.date.available2017-12-06T08:58:48Z
dc.date.issued2010
dc.identifier.doi10.1007/BF03345438
dc.identifier.pissn0724-5319
dc.identifier.urihttps://dl.gi.de/handle/20.500.12116/8528
dc.language.isoen
dc.publisherGesellschaft für Informatik e.V.
dc.relation.ispartofFERS-Mitteilungen: Vol. 28, No. 1
dc.relation.ispartofseriesFERS-Mitteilungen
dc.subjectRegister File
dc.subjectFault Injection
dc.subjectSoft Error
dc.subjectRISC Processor
dc.subjectSuperscalar Processor
dc.titleA Fault-Tolerant Processor Architectureen
dc.typeText/Journal Article
gi.citation.endPage19
gi.citation.startPage14

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FERS-Mitteilungen 28(1) - 2010